Interconnection for preventing signal interference in a semicond

Details Interconnection for preventing signal interference in a semicond Interconnection for preventing signal interference in a semicond

1998-10-14

2000-12-26

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257756, 257757, 257759, H01L 23552

Patent

active

061664405

ABSTRACT:
A vertical or parallel interconnection structure in a semiconductor device wherein a shielding means is provided to prevent signal coupling between signal lines having small swing signals and noise sensitive signals. The shielding means is disposed between the signal lines and parallel with them and driven by power source of stable level, for example a ground voltage, a power supply voltage, or a DC voltage of arbitrary level.

REFERENCES:
patent: 5585664 (1996-12-01), Ito
LeCoz et al., "A Stochastic Algorithm for High Speed Capacitance Extraction in Integrated Circuits," Solid State Electronics, vol. 35, No. 7, pp. 1005-1012, 1992.
Basel, "Accurate and Efficient Extraction of Interconnect Circuits for Full-Chip Timing Analysis," pp. 118-123, 1995.
Huang et al., "Accurate Modeling of Capacitive, Resistive and Inductive Effects of Interconnect," pp. 115-117.
Ruehli et al., "Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems," IEEE Transactions on Microwave Theory and Techniques, vol. MTT-21, No. 2, pp. 76-82, Feb. 1973.
Huang, "Two-Dimensional Capacitance Calculation in Stratified and/or Arbitrary Dielectric Media," IEEE Transactions on Microwave Theory and Techniques, vol. 42, No. 3, pp. 501-504, Mar. 1994.

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