Integration of low-K SiOF as inter-layer dielectric for AL-gapfi

Details Integration of low-K SiOF as inter-layer dielectric for AL-gapfi Integration of low-K SiOF as inter-layer dielectric for AL-gapfi

1998-01-15

2000-12-26

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257636, 257638, 438784, 438788, H01L 2358, H01L 2131, H01L 21469

Patent

active

061664278

ABSTRACT:
A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

REFERENCES:
patent: 5703404 (1997-12-01), Matsura
patent: 5753975 (1998-05-01), Matsuno
patent: 5789315 (1998-08-01), Besser et al.
patent: 5872065 (1999-02-01), Sivaramakrishnan
patent: 5913140 (1999-06-01), Roche et al.
patent: 5994778 (1999-11-01), Huang et al.

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