Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1995-02-07

1995-12-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, 365207, 365203, 36518906, 36518911, G11C 700, G11C 11409

Patent

active

054774985

ABSTRACT:
A sense amplifier including a pair of NMOS transistors connected in series between a pair of bit lines differential-amplifies the potential difference between the pair of bit lines by reducing the source potentials of the NMOS transistors to ground potential. An NMOS transistor is activated for a predetermined time after initiation of a differential amplification by the sense amplifier, whereby the source potentials of the NMOS transistors are controlled so as to attain a potential lower than the ground potential during that predetermined time. As a result, the operation margin of the NMOS transistors is increased during the predetermined time period.

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patent: 5313426 (1994-05-01), Sakuma et al.
patent: 5325335 (1994-06-01), Ang et al.
Okamura et al., "DEcoded-Source Sense Amplifier for High-Density DRAM's", IEEE Journal of Solid-State Circuits, vol. 25, No. 1 (Feb. 1990), pp. 18-23.
Kawahara et al.,"A Circuit Technology for Sub-10-NS ECL 4-MB BICMOS DRAM's" IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1530-1537.
Tachibana et al., "Design of Overdrive Sense Amplifier for High-Speed DRAM," IEEE J. Solid-State Circuits, Nov. 1991, pp. 5-153.
Horiguchi et al., "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier," 1990, pp. 75-76.

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