Memory device

Static information storage and retrieval – Systems using particular element – Semiconductive

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365177, 365154, 365156, 365129, G11C 1140

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054774837

ABSTRACT:
The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.
A memory device structuring a memory cell by connecting the follows: i) the first transistor of PNP type, having connection of input voltage to its base and grounding an emitter; ii) the second transistor of NPN type having connection of base to a collector of the first transistor, grounding collector and connection of power source to an emitter; and iii) the collector of the second transistor to the base of the first transistor.

REFERENCES:
patent: 4366554 (1982-12-01), Aoki et al.
patent: 4455625 (1984-06-01), Denis et al.
patent: 4922411 (1990-05-01), Hobbs
patent: 4943740 (1990-07-01), Gulczynski
Pricer, David, "Integrated Circuits" (RAM, ROM), The Electrical Engineering Handbook, Editor-In-Chief, Richard C. Dorf., CRC Press, 1993, pp. 1651-1657.
Patent Abstracts of Japan, vol. 001, No. 136, 10 Nov. 1977 & JPP-A-51 120 141 (Tokyo Shibaura Electric).

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