System and method for enabling and disabling writeback cache

Details System and method for enabling and disabling writeback cache System and method for enabling and disabling writeback cache

1996-07-25

1998-05-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, G06F 1212

Patent

active

057522626

ABSTRACT:
A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.

REFERENCES:
patent: 4685082 (1987-08-01), Cheung et al.
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5414827 (1995-05-01), Lin
patent: 5423019 (1995-06-01), Lin
patent: 5469555 (1995-11-01), Ghosh et al.

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