Structure for cross coupled thin film transistors and static ran

Details Structure for cross coupled thin film transistors and static ran Structure for cross coupled thin film transistors and static ran

1998-08-19

2000-04-25

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257394, 257381, 257359, 257368, 257903, H01L 2976, H01L 2974, H01L 31062

Patent

active

060547421

ABSTRACT:
A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V.sub.cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V.sub.cc through the first TFT.

REFERENCES:
patent: 5278459 (1994-01-01), Matsui et al.
patent: 5286663 (1994-02-01), Manning
patent: 5422499 (1995-06-01), Manning
patent: 5440508 (1995-08-01), Pathak et al.
patent: 5471071 (1995-11-01), Yoshihara
patent: 5818090 (1998-10-01), Kimura

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