Single polysilicon flash EEPROM with low positive programming an

Details Single polysilicon flash EEPROM with low positive programming an Single polysilicon flash EEPROM with low positive programming an

1998-01-30

2000-04-25

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, 257324, H01L 2976, H01L 2988, H01L 29792

Patent

active

060547324

ABSTRACT:
A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N.sup.+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N.sup.+ control gate (26). N.sup.+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

REFERENCES:
patent: 5465231 (1995-11-01), Ohsaki
patent: 5501996 (1996-03-01), Yang et al.
A Scaled 0.6 .mu.m High Speed PLD Technology Using Single-Poly EEPROM's: Adam et al. IEEE Custom Integratet Circuits Conference, 1995.
A New Single-poly Flash Memory Cell with Low-Voltage and Low-power Operation for Embeded Applications: Chi et al. Advanced Technology Group, National Semiconductor Cor (408)-721-5390.
High Robust 0.25 .mu.m Single-poly-gate CMOS with Inter-Well deep Trenches. Inokawa et al. 1996 Symposium on VLSI Technology Digest of Technical Papers, 1996.
Single Poly Cell as the Best Choice for Radiation-Hard Floating Gate EEPROM Technology. Wellekens et al. IEEE Transactions on Nuclear Science, vol. 40, No. 6, Dec. 1993.

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