Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1999-11-18
2000-12-26
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438265, 438696, 257900, H01L 213205
Patent
active
061658839
ABSTRACT:
A gate electrode having a polymetal structure which is composed of polysilicon, tungsten nitride and tungsten is formed on a silicon substrate by RIE where a silicon nitride film is used as a mask. Thereafter, a silicon oxide film of about 3 nm is formed by selective oxidation, and a silicon nitride film of about 10 nm is formed by CVD. Moreover, the silicon nitride film is etched by using the silicon substrate as an etching stopper. Thereafter, a silicon oxide film of about 6 nm is formed again by thermal oxidation, and a silicon nitride film of about 20 nm is formed by CVD. Then, the silicon nitride film is etched by using the silicon oxide film as an etching stopper.
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IEDM Technical Digest, "Integration Technorology of Polymetal (W/WSiN/Poly-Si) Dual Gate CMOS for 1Gbit DRAMs and Beyond", p. 389, Yohei Hiura et al., 1998.
Bowers Charles
Kabushiki Kaisha Toshiba
Kielin Erik
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