MOS random access memory having array of trench type one-capacit

Details MOS random access memory having array of trench type one-capacit MOS random access memory having array of trench type one-capacit

1995-04-07

1995-12-19

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, H01L 2968, H01L 2978, H01L 2992

Patent

active

054770718

ABSTRACT:
A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

REFERENCES:
patent: 4791463 (1988-12-01), Malhi
patent: 4864375 (1989-09-01), Tang et al.
patent: 4914739 (1990-04-01), Malhi
patent: 4939104 (1990-07-01), Pollack et al.
patent: 5225697 (1993-07-01), Malhi et al.
IEDM Tech. Dig., 1985, pp. 714-717, W. F. Richardson, A Trench Transistor Cross-Point DRAM Cell.
ISSCC91, pp. 106-107, 297, K. Kimura, "A Block-Oriented RAM with Half-Sized . . . ".

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