Semiconductor memory device

Static information storage and retrieval – Read/write circuit – For complementary information

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Details

365208, 36518909, 36523006, 36523008, G11C 700

Patent

active

054405122

ABSTRACT:
A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

REFERENCES:
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patent: 4376989 (1983-03-01), Takemae
patent: 4385369 (1983-05-01), Sheppard
patent: 4393480 (1983-07-01), Shimada
patent: 4888737 (1989-12-01), Sato
patent: 4951259 (1990-08-01), Sato et al.
patent: 4965770 (1990-10-01), Yanagisawa
patent: 5105389 (1992-04-01), Matsuo et al.

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