Semiconductor device having an SOI structure and a manufacturing

Details Semiconductor device having an SOI structure and a manufacturing Semiconductor device having an SOI structure and a manufacturing

1994-07-26

1995-08-08

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257350, 257351, 257398, 257400, 437 21, 437 40, 437 56, 437 61, H01L 2701, H01L 2906, H01L 21265

Patent

active

054401615

ABSTRACT:
A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.

REFERENCES:
"Shielded Silicon Gate Complementary MOS Integrated Circuit", Hung Chang Lin et al., IEEE Transactions on Electron Devices, vol. ED-19, No. 11, Nov. 1972, pp. 1199-1206.
"CAD-Compatible High-Speed CMOS/SIMOX Technology Using Filed-Shield Isolation for 1M Gate Array", T. Iwamatsu et al., IEEE 1993.
Physics of Semiconductor Devices, S. M. Sze.

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