Low jitter phase detector for phase locked loops

Details Low jitter phase detector for phase locked loops Low jitter phase detector for phase locked loops

1996-06-24

1998-09-15

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

329303, 329307, 331 1R, 331 1A, H04L 2710

Patent

active

058090975

ABSTRACT:
A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5027085 (1991-06-01), DeVito
patent: 5271040 (1993-12-01), Clark
patent: 5631590 (1997-05-01), Tomesakai
Hogge, Jr., Charles R. Journal Of Lightwave Technology, vol. LT-3, No. 6, Dec. 1985 "A Self Correcting Clock Recovery Circuit," pp. 1312-1314.
Lee, Thomas H. et al., IEEE Journal Of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, "A 155-MHz Clock Recovery Delay-and Phase-Locked Loop," pp. 1736-1745.
"Self-Correcting Clock Recovery Circuit With Improved Jitter Performance," Electronics Letter, 29 Jan. 1987, vol. 23 No. 3, pp. 110-111.

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