Input circuit with improved operating margin using a single inpu

Details Input circuit with improved operating margin using a single inpu Input circuit with improved operating margin using a single inpu

1997-12-04

2000-12-05

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 23, 326 34, 326 68, 326 83, 361111, H03K 19003, H03K 190175, H02H 322

Patent

active

061572039

ABSTRACT:
A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.

REFERENCES:
patent: 5019729 (1991-05-01), Kimura et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5659513 (1997-08-01), Hirose et al.
patent: 5796281 (1998-08-01), Saeki et al.
Electronic-Industries-Association-of-Japan Standards EIAJ ED-5512, Mar., 1996 and English translation.

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