Semiconductor memory device having a plurality of memory cell tr

Details Semiconductor memory device having a plurality of memory cell tr Semiconductor memory device having a plurality of memory cell tr

1998-01-16

2000-12-05

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

36518517, 438258, H01L 29708, H01L 21336, G11C 1604

Patent

active

061570567

ABSTRACT:
The semiconductor memory device comprises first and second memory cell rows each constructed by connecting a plurality of memory cell transistors, and third and fourth memory cell rows which are provided to be respectively adjacent to the first and second memory cell rows, such that element separation regions are respectively provided between adjacent memory cell rows. First and second transistors are connected between a drain or a source of the first memory cell row and a drain or a source of the second memory cell row. Gate electrodes of the first and third transistors are connected by a first gate line, and gate electrodes of the second and fourth transistors are connected by a second gate line. The first and second transistors are connected to a data line by a first contact. The third and fourth transistors are connected to a data line by a second contact. A first spacing element is connected between the first and second transistors and a second spacing element is connected between the third and fourth transistors, so that the distance between the first and second contacts is widened. The first contact is provided between the first transistor and the first spacing element. The second contact is provided between the fourth transistor and the second spacing element. The first spacing element is connected through the third gate line to the second spacing element.

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patent: 5680347 (1997-10-01), Takeuchi et al.
patent: 5682350 (1997-10-01), Lee et al.
patent: 5698879 (1997-12-01), Aritome et al.

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