Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-08-22
2000-12-05
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438648, 438656, 438682, 438683, 438685, H01L 213205, H01L 214763
Patent
active
061566306
ABSTRACT:
A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.
REFERENCES:
patent: 4933743 (1990-06-01), Thomas et al.
patent: 5086016 (1992-02-01), Brodsky et al.
patent: 5117276 (1992-05-01), Thomas et al.
patent: 5173327 (1992-12-01), Sandhu et al.
patent: 5210431 (1993-05-01), Kimoto et al.
patent: 5330921 (1994-07-01), Yoshida et al.
patent: 5439833 (1995-08-01), Herbert et al.
patent: 5721175 (1998-02-01), Kunishima et al.
patent: 5745990 (1998-05-01), Lee et al.
patent: 5827762 (1998-10-01), Bashir et al.
patent: 5858873 (1999-01-01), Vitkavage et al.
patent: 5882992 (1999-03-01), Kobeda et al.
patent: 5898221 (1999-04-01), Mizuhara et al.
patent: 5911114 (1999-06-01), Naem
patent: 5913139 (1999-06-01), Hashimoto et al.
patent: 5918145 (1999-06-01), Rodder
patent: 5981372 (1999-11-01), Goto et al.
patent: 5985713 (1999-11-01), Bailey
patent: 5990513 (1999-11-01), Perino et al.
patent: 5994730 (1999-11-01), Shrivastava et al.
Choi et al "Optimization and characterization of LPCVD TiB(sub2) for ULSI applications," J. Electrochem. Soc. vol. 138, No. 10, pp. 3053-3061, Oct. 1991.
Williams, "Plasma enhanced chemical vapor deposition of titanium boride films," APL, vol. 46, Iss. 1, pp. 43-45, Jan. 1, 1985.
Pelleg et al "Titanium silicide formation in TiSi(sub2)/TiB(sub2) bilayer barrier layer structure," Microelectronic Engineering, vol. 33, Iss. 1-4, pp. 317-323, Jan. 1997.
Sade et al "Sputter deposition and characterization of TiB(sub2)/TiSi(sub2) bilayer contact structure," MAM 97--Materials for Advanced Metalization Poster Session II, pp. 210-212, 1997.
Choi et al "Stability of TiB(sub2) as a diffusion barrier on silicon," J. Electochem. Soc., vol. 138, No. 10, pp. 3062-3067, Oct. 1991.
Choi et al "Optimization and characterization of LPCVD TiB(sub2) for ULSI applications," J. Electrochem. Soc. vol. 138, No. 10, pp. 3053-3061, Oct. 1991.
C.S. Choi et al., "Transactions on Electron Devices", IEEE, 39, 2341-2345 (1992).
Hack Jonathan
Micro)n Technology, Inc.
Niebling John F.
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