Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

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365226, G11C 800, G11C 700

Patent

active

059094060

ABSTRACT:
Memory cell arrays, in which memory cells are arranged in a matrix, are divided into a plurality of blocks. In a semiconductor memory device having the memory cell arrays, load circuits are connected to bus lines and the memory cell arrays. The number of load circuits is the same as that of the memory cell arrays. Thus, the load circuits function to supply the same amount of current to the bus lines, whatever block is activated in a writing operation. Therefore, writing characteristics of all the memory cell array blocks are the same.

REFERENCES:
patent: 5136546 (1992-08-01), Fukuda et al.
patent: 5553026 (1996-09-01), Nakai et al.
patent: 5579260 (1996-11-01), Iwahashi

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