Semiconductor memory

Details Semiconductor memory Semiconductor memory

1997-02-12

1998-09-15

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

36518907, 36518905, 371 211, G11C 700

Patent

active

058089497

ABSTRACT:
A semiconductor memory comprising memory cells, a write buffer, a write inversion gate, a data input terminal, and four write data buses 1-4. The write buffer and the write inversion gate place onto two write data buses 1 and 3 the data input through the data input terminal. The inverted data of the input data is output onto two other write data buses 2 and 4. This causes alternately different data to be written to four contiguous memory cells. The scheme permits detection of a cell fault caused by interference between contiguous memory cells.

REFERENCES:
patent: 5400281 (1995-03-01), Morigami
patent: 5400342 (1995-03-01), Matsumura et al.
patent: 5548596 (1996-08-01), Tobita
patent: 5631870 (1997-05-01), Arimoto
"A 90NS 1 MB DRAM with Multi-Bit Test Mode", Kumanoya et al., ISSCC85 Digest of Technical Papers, pp. 240-241.
German Patent Office Action dated Dec. 30, 1996 and English translation thereof.

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