Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Including signal clamping

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365190, G11C 700

Patent

active

048294772

ABSTRACT:
A semiconductor memory device is provided with a clamp circuit for clamping a driving level of a write circuit so that the information on a bit line can be transmitted quickly to a data bus at the time of a read-out operation by using transistors having a low threshold value (or a large mutual conductance) for the transistors constituting a column transfer gate, and so that a write-in operation can be carried out at a high speed by using transistors having a large mutual conductance for driving transistors of the write circuit and setting a required level by clamping the driving level of the write circuit.

REFERENCES:
patent: 4062000 (1977-12-01), Donnelly
patent: 4386419 (1983-05-01), Yamamoto

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