Method and apparatus for controlling a digital phase lock loop a

Details Method and apparatus for controlling a digital phase lock loop a Method and apparatus for controlling a digital phase lock loop a

1995-03-06

1997-01-28

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 25, 327105, H03D 324

Patent

active

055984487

ABSTRACT:
A digital phase lock loop controller (DPLL) (10) incorporates an adjustment generator (34) for continually adjusting the sensitivity of the DPLL (10) to reduce injected noise. The DPLL also comprises an error detector (16), a frequency adjuster (22), a first oscillation generator (28), and a divider (32) that function in a manner common to many DPLLs (10). However, the adjustment generator (34) continually adjusts the operation of the frequency adjuster (22) based upon the relative phase difference between a reference oscillation (12) and a feedback oscillation (14) in order to vary the sensitivity of the DPLL (10). When the reference oscillation (12) and the feedback oscillation (14) are relatively in phase, the sensitivity of the DPLL (10) is low. Oppositely, when the reference oscillation (12) and the feedback oscillation (14) move out of phase, the sensitivity of the DPLL (10) increases.

REFERENCES:
patent: 4506233 (1985-03-01), Englund, Jr.
patent: 4758801 (1988-07-01), Draxelmayr
patent: 4931748 (1990-06-01), McDermott et al.
patent: 5220294 (1993-06-01), Ichikawa
patent: 5347233 (1994-09-01), Ishibashi et al.
patent: 5436937 (1995-07-01), Brown et al.

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