Information processing device and control method thereof

Details Information processing device and control method thereof Information processing device and control method thereof

1996-08-20

2000-02-01

Teska, Kevin J.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1208

Patent

active

060214724

ABSTRACT:
An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY block in the cache memory is started. The cache memory issues a bus transaction onto a system bus and performs write back of the DIRTY block in the cache memory relative to a main memory. The write back bus transaction issued from the cache memory in the foregoing fashion is snooped by the other cache memory. With this arrangement, an unnecessary consistency holding operation can be omitted to reduce a delay upon memory accessing in a parallel computer system employing a loose memory consistency model.

REFERENCES:
patent: 5222224 (1993-06-01), Flynn et al.
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5313609 (1994-05-01), Baylor et al.
patent: 5386546 (1995-01-01), Hamaguchi
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5577218 (1996-11-01), Hamaguchi

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