Method for reducing power consumption in a set associative cache

Details Method for reducing power consumption in a set associative cache Method for reducing power consumption in a set associative cache

1999-02-04

2000-02-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711128, 713324, G06F 1206

Patent

active

060214619

ABSTRACT:
A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The method also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.

REFERENCES:
patent: 5029126 (1991-07-01), Yamaguchi
patent: 5691956 (1997-11-01), Chang et al.
patent: 5715426 (1998-02-01), Takahashi et al.
patent: 5778428 (1998-07-01), Batson et al.
patent: 5783958 (1998-07-01), Lysinger
patent: 5784712 (1998-07-01), Byers et al.
patent: 5848428 (1998-12-01), Collins
patent: 5918044 (1999-06-01), Levitan et al.

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