Static RAM memory cell

Details Static RAM memory cell Static RAM memory cell

1980-12-24

1983-04-12

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365203, G11C 706

Patent

active

043800556

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to random access memories, and more particularly to a static MOS random access memory cell utilizing no sense amplifiers.


BACKGROUND ART

Large scale integration techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. The storage cells, typically using MOS technology, consist of multicomponent circuits in a conventional bistable configuration. There are numerous advantages of such semiconductor storage devices including high packing density and low power requirements of such memory cells.
Numerous prior art static memory cells of an integrated circuit memory have been developed. A well known static memory cell circuit arrangement which utilizes six insulated gate MOS field-effect transistors is a cross-coupled inverter stage shown in U.S. Pat. No. 3,967,252 issued to Donnelly on June 29, 1976 and entitled "Sense Amp for Random Access Memory". Because of the relatively small capacitance of the cells compared to the capacitance of the column line, the voltage swing is usually small requiring the use of sense amplifier circuits to detect this small voltage swing on a column line. Such a sense amplifier is disclosed in the above referred to Donnelly patent. The use of sense amplifiers substantially complicates the fabrication and operation of a static memory cell.
A need has thus arisen for a static RAM cell in which data stored therein can be read by reading the logic levels stored therein without the use of sense amplifers. A need has further arisen for a low voltage operating static RAM cell operating with minimal quiescent current and which utilizes an X-Y addressing technique.


DISCLOSURE OF THE INVENTION

In accordance with the present invention, a static random access memory cell is provided having improved read out capabilities, operating at low voltage with low quiescent current.
In accordance with the present invention, a memory cell for storing data having a data signal line and a bit signal line for receiving control signals, first and second control lines for receiving control signals and a cell voltage supply source is provided. A first transistor is interconnected to the data signal line and to the bit signal line and is activated by a control signal. A second transistor is provided and is connected to the first transistor and to the first control line for being activated by a control signal. A third transistor is provided and is connected to the first transistor and to the second control line for being activated by a control signal. A first inverter is coupled to the cell voltage supply and to the second and third transistors. A second inverter is coupled to the cell voltage supply and to the second and third transistors. The first and second inverters are cross-coupled to the second and third transistors for storing date within the memory cell.


BRIEF DESCRIPTION OF DRAWINGS

For a more complete understanding of the present invention and for further advantages thereof, reference will now be made to the following Detailed Description taken in conjunction with the accompanying Drawings in which:
FIG. 1 is a schematic circuit diagram of the memory cell of the present invention; and
FIG. 2 is a schematic diagram of the cross-coupled inverters illustrated in FIG. 1.


DETAILED DESCRIPTION

Referring to FIG. 1, the memory cell of the present invention is illustrated and is generally identified by the numeral 10. Memory cell 10 is utilized as part of an array of numerous such cells arranged in rows and columns in a conventional manner to form a random access memory. The random access memory thereby formed using memory cell 10 may be fabricated on a single semiconductor chip and is primarily intended for such fabrication utilizing metal-oxide-semiconductor technology.
When arranged in an array of memory cells, memory cells 10 are interconnected to a common data line 12. Data stored within a memory cell 10 is read from memory cell 10 via data line 12 which is initially precharged using a data line

REFERENCES:
patent: 3967252 (1976-06-01), Donnelly
patent: 4193127 (1980-03-01), Gersbach
patent: 4272811 (1981-06-01), Wong

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