Static type semiconductor memory device and method of manufactur

Details Static type semiconductor memory device and method of manufactur Static type semiconductor memory device and method of manufactur

1991-04-30

1992-11-24

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257903, 257387, 257395, H01L 2906, H01L 2978, H01L 2702, H01L 2904

Patent

active

051667630

ABSTRACT:
A static type semiconductor memory device includes memory cells each including a pair of field effect transistors (FETs) each having a gate electrode cross-coupled to a drain region connected to a power source terminal by way of a load register. The memory device includes a semiconductor substrate of a first conductivity type, polycrystal silicon layers containing impurities of a second conductivity type and first and second FETs. The polycrystal silicon layers are formed with a spacing from one another for defining a channel region on the substrate. The first and second FETs are formed on the substrate and each includes source and drain regions of a second conductivity type and a gate electrode. The source and drain regions are formed below the polycrystal silicon layers by introducing impurities from the polycrystal silicon layers into the substrate. The gate electrode is formed on the channel region and the polycrystal silicon layers with a gate insulating film interposed. The drain region of the first FET and the gate electrode of the second FET are cross-coupled to each other through the polycrystal silicon layer, while the drain region of the second FET and the gate electrode of the first FET are also similarly cross-coupled to each other. The parasitic resistance of the source and drain regions can be reduced, while the leakage current due to the short channel effect can also be reduced. Since the memory cell is freed of asymmetries, a static type semiconductor memory device is provided with is improved both in stability and data storage property.

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C. S. Oh et al, "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes" IEEE Electron Device Letters, vol. EDL-5, No. 10, October 1984, pp. 400-402.
M. K. Moravvei-Farshi et al, "Effects of Interfacial Oxide Layer on Short-Channel Polycrystalline Source and Drain MOSFET's" IEEE Electron Device Letters, vol. EDL-8, No. 4, April 1987, pp. 165-167.
Tiao-Yuan Huang et al, "A MOS Transistor with Self-Aligned Polysilicon Source Drain" IEEE Electron Device Letters, vol. EDL-7, No. 5, May 1986, pp. 314-316.

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