Method for manufacturing a semiconductor random access memory ce

Details Method for manufacturing a semiconductor random access memory ce Method for manufacturing a semiconductor random access memory ce

1990-12-14

1992-11-24

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437191, 437193, 437233, 437235, 437919, H01L 2170

Patent

active

051660903

ABSTRACT:
There is disclosed a method for easily manufacturing a semiconductor random access memory cell having a large stacked storage capacitance. The inventive subject, to attain the goal of the invention, includes steps of: forming a thick field oxide layer on a portion of the semiconductor surface; forming an N+ drain region on the semiconductor substrate surface; forming a gate oxide layer on the surface the drain, source and channel regions; forming a first conductive polycrystalline silicon layer on the upper portion channel region and a given portion of said field oxide layer, respectively; forming a first insulating layer, a first cell plate layer, a first dielectric layer, and a second polycrystalline silicon layer on a word line, the exposed gate oxide layer and the field oxide layer; forming a contact hole within the first insulating layer, the first cell plate layer, a first dielectric layer, and the second polycrystalline silicon layer on the drain region; forming a side wall-insulating layer defined to a side wall of said contact hole; forming a third polycrystalline silicon layer on the exposed source region and side-wall insulating layer; forming a second dielectric layer on a surface of the exposed cell node layer after removing the given portion of the first and second polycrystalline silicon layers; and forming a second cell plate of a fourth polycrystalline silicon layer on the upper portion of the second dielectric layer.

REFERENCES:
patent: 4641166 (1987-02-01), Takemae
patent: 4700457 (1987-10-01), Matsukawa
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 4899203 (1990-02-01), Ino

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