Semiconductor memory device incorporating a test mode therein to

Static information storage and retrieval – Read/write circuit – Testing

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Details

365222, 36518904, G11C 1300

Patent

active

055026770

ABSTRACT:
There is provided a switch 140 between an address line 121 and external output terminals A0.about.An, controlled by outputs of a counter circuit 117 and a test mode control circuit 119. The switch 140 transfers a variation of an address signal to external output terminals A0.about.An, without connecting the address line 121 with the external address terminals A0.about.An, directly.

REFERENCES:
patent: 5161120 (1992-11-01), Kajimoto et al.
patent: 5416740 (1995-05-01), Fujita et al.

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