Method of constructing reduced size highly integrated static ran

Details Method of constructing reduced size highly integrated static ran Method of constructing reduced size highly integrated static ran

1994-03-09

1994-12-27

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257379, 257385, 257903, H01L 2702, H01L 2910, H01L 2978

Patent

active

053768140

ABSTRACT:
A static random access memory with a double vertical channel structure capable of providing a highly integrated memory element and a method of the same. On a substrate of a first conductivity type, first and second layers of the same conductivity type are formed, in order. On respective surfaces of the three layers, impurity diffusion regions are formed, centers of which are located on a vertical line. The first layer having the second impurity diffusion region and the second layer having the third impurity diffusion region are removed at their center portions, except for their opposite side portions, thereby forming trenches. In these trenches, gate electrodes and a ground electrode are formed. Accordingly, the first impurity diffusion region and the remaining opposite side portions of second and third impurity diffusion regions become source/drain regions, while the remaining opposite side portions of first and second layers become a double vertical channel region.

REFERENCES:
patent: 4829017 (1989-05-01), Malhi
patent: 4914058 (1990-04-01), Blanchard
patent: 4920065 (1990-04-01), Chin et al.

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