Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1997-05-08

1998-09-15

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257318, 36518525, H01L 29788

Patent

active

058083383

ABSTRACT:
An N well and an n-type ground wiring layer are formed in a P-substrate by diffusion. A word line consisting of p-type polysilicon is formed in the N well. The drain and source regions of a memory cell transistor are formed near the N well by ion-implanting arsenic into the P-substrate. A continuous floating gate is formed on the channel region between the drain and source regions and the word line region through a predetermined gap. The p-type silicon portion opposing this floating gate serves as the control gate of the memory cell transistor. When a pulse alternately and repeatedly having potentials of +3 V and -10 V is applied to the word line, the thresholds of the corresponding memory cell transistors converge to a value corresponding to +3 V of the pulse.

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