Semiconductor memory device having stacked memory capacitors and

Details Semiconductor memory device having stacked memory capacitors and Semiconductor memory device having stacked memory capacitors and

1988-02-19

1989-08-08

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, 357 40, G11C 1300, G11C 1140

Patent

active

048559539

ABSTRACT:
A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.

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