Method to form ultra-short channel elevated S/D MOSFETS on an ul

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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438307, 438589, H01L 228232

Patent

active

059565802

ABSTRACT:
The method includes forming a buried oxide layer in a substrate. A pad oxide layer is then form on the substrate. A silicon nitride layer is pattered on the surface of the pad oxide. Then, a thick field oxide (FOX) is formed on the pad oxide layer. Sidewall spacers are formed on the side walls of the opening of the silicon nitride layer. Next, the FOX is etched. An ion implantation is performed for adjusting the threshold voltage and anti-punch-through implantation. Subsequently, a thin silicon oxynitride layer is deposited on the surface of the silicon nitride, spacers and the opening. A polysilicon gate is then formed in the opening. Then, Then, the silicon oxynitride layer, silicon nitride and the spacers are removed. Source and drain are next created. The pad oxide layer and the FOX are then removed. Then, the lightly doped drain (LDD) are formed. Self-aligned silicide (SALICIDE) layer, polycide layer are respectively formed on the substrate exposed by the gate, and on the gate.

REFERENCES:
patent: 5552329 (1996-09-01), Kim et al.
patent: 5583064 (1996-12-01), Lee et al.
patent: 5877048 (1999-03-01), Wu
patent: 5877056 (1999-03-01), Wu

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