Method and system for inhibiting transfer of duplicate write add

Details Method and system for inhibiting transfer of duplicate write add Method and system for inhibiting transfer of duplicate write add

1996-08-26

1999-07-06

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395280, 395293, 39520075, 39520046, 711124, G06F 1300, G06F 1340

Patent

active

059208929

ABSTRACT:
A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module provides a match filter which prevents the passage from one bus to the other bus of a duplicate Write operation (OP) address which has already been transferred, thus relieving the busses of excess traffic when a duplicate Write OP address is being sent to a cache memory for an invalidation operation. A Read operation will nullify the match filter to then allow passage of each incoming Write OP invalidation address to the snoop invalidation queue, but prevent the passage of a subsequent duplicate Write OP address, so long as the read OP is ongoing.

REFERENCES:
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5446848 (1995-08-01), Whitlock et al.
patent: 5696937 (1997-12-01), White et al.
patent: 5761445 (1998-06-01), Nguyen

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