Register-based redundancy circuit and method for built-in self-r

Details Register-based redundancy circuit and method for built-in self-r Register-based redundancy circuit and method for built-in self-r

1997-09-26

1999-07-06

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 371 225, 371 103, G11C 700

Patent

active

059205156

ABSTRACT:
A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.

REFERENCES:
patent: 4388705 (1983-06-01), Sheppard
patent: 5563826 (1996-10-01), Pascucci et al.
patent: 5642308 (1997-06-01), Yoshida
patent: 5771191 (1998-06-01), Matsue

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