Multi-stage ROM structure

Details Multi-stage ROM structure Multi-stage ROM structure

1998-06-12

1999-07-06

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, 257392, 438276, H01L 2976, H01L 2994

Patent

active

059201002

ABSTRACT:
A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole in an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding process. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a spacer on the opposite side-walls of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

REFERENCES:
patent: 4663644 (1987-05-01), Shimizu
patent: 5300804 (1994-04-01), Arai
patent: 5736771 (1998-04-01), Huang et al.

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