Method and system for maintaining strong ordering in a coherent

Details Method and system for maintaining strong ordering in a coherent Method and system for maintaining strong ordering in a coherent

1996-09-27

1999-07-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711158, G06F 1318

Patent

active

059308222

ABSTRACT:
A method and system of maintaining strong ordering in a multiprocessor computer system having a coherent memory. Memory transactions are send from one or more processors to a processor agent. The processor agent sends the transactions to a memory agent via a crossbar switch. The memory agent performs memory coherency operations and sends memory transactions back to the processor agents via the crossbar switch. The crossbar switch, however, may alter the order in which the memory transactions are forwarded to the processor agent. Therefore, the memory agent also sends a timestamp for each memory transaction directly to the processor agent via a dedicated link. An arbitrator within the processor agent receives the timestamps and the memory transactions. Using the timestamps, the arbitrator reorders the memory transactions and sends the transactions to the processors in the order in which the transactions were sent. In addition, the memory agent sends a parity signal with each timestamp. Specific combinations of parity signals and timestamps tell the arbitrator the type of transaction it will receive from the memory agent. Dependent upon the type of transaction, the arbitrator can change the order in which the transactions are sent to the processors.

REFERENCES:
Stenstrom, "A Latency--Hiding Scheme for Multiprocessors with Buffered Multistage Networks", 1992, pp. 39-42, IEEE.

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