Multilayered interconnection substrate and process for fabricati

Details Multilayered interconnection substrate and process for fabricati Multilayered interconnection substrate and process for fabricati

1997-02-07

1999-07-27

Codd, Bernard

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438710, 438738, 438745, 438763, 430314, 430317, 216 18, 216 19, G03C 500

Patent

active

059306769

ABSTRACT:
A multilayered interconnection substrate prevents contact failure from occurring and a process for fabricating the same wherein a multilayered interconnection substrate comprises a first interconnection layer formed on a substrate, at least two layers of insulation films differing in composition from each other are formed on the first interconnection layer. The insulation layers have at least one contact hole formed in such a manner to expose the selected portion of the first interconnection layer. A resin wall buries stepped portions formed on an inter-peripheral portion of the contact hole and a second interconnection layer formed inside the contact hole along the resin wall which is electrically connected to the first interconnection layer exposed at the bottom portion of the contact hole.

REFERENCES:
patent: 5117273 (1992-05-01), Stark et al.
patent: 5138424 (1992-08-01), Moss et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5231751 (1993-08-01), Sachdev et al.
patent: 5408130 (1995-04-01), Woo et al.

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