Integrated circuit having improved polysilicon resistor structur

Details Integrated circuit having improved polysilicon resistor structur Integrated circuit having improved polysilicon resistor structur

1995-12-12

1998-11-17

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257377, 257379, 257538, H01L 2900

Patent

active

058380442

ABSTRACT:
A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

REFERENCES:
patent: 4609835 (1986-09-01), Sakai et al.
patent: 4727045 (1988-02-01), Cheung et al.
"VLSI Technology, " 1988, McGraw-Hill Book Company, Murray Hill, NJ X-002022719, pp. 382-384, 480, ed. Sze.

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