Semiconductor memory device capable of realizing a minimum memor

Details Semiconductor memory device capable of realizing a minimum memor Semiconductor memory device capable of realizing a minimum memor

1996-11-08

1998-11-17

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, H01L 27108

Patent

active

058380361

ABSTRACT:
In semiconductor memory device, word lines (2a) are arranged in parallel to each other on a semiconductor substrate (9). Each of the device active regions (1) has first oblique intersection portions (1a) which obliquely intersect adjacent two of the word lines (2a) in first oblique directions with a distance left between each of the device active regions (1) and the adjacent two of the word lines (2a). Each of bit lines (4) has second oblique intersection portions (4a) which obliquely intersect the adjacent two of the word lines (4) in second oblique directions reverse with respect to the first oblique directions with another distance left between each of the bit lines (4) and the adjacent two of the word lines (2a). The first oblique directions of the first oblique intersection portions (1a) of each of the device active regions (1) are reversed at every memory cell (or at every two memory cells). The second oblique directions of the second oblique intersection portions (4a) of each of the bit lines (4) are reversed at every memory cell (or at every two memory cells).

REFERENCES:
patent: 5014103 (1991-05-01), Ema
patent: 5363326 (1994-11-01), Nakajima
patent: 5391901 (1995-02-01), Tanabe
patent: 5583358 (1996-12-01), Kimura et al.
patent: 5604365 (1997-02-01), Kajigaya et al.
Eimori et al; "A Newly Designed Planar Stacked Capacitor Cell with High dielectric Constant Film for 256Mbit DRAM"; 1993; pp. 631-634; IEDM Tech. Dig.
Shibahara et al; "lGDRAM Cell with Diagonal Bit-Line (DBL) Configuration and Edge Operation MOS (EOS) FET"; 1994; pp. 639-642; IEDM Tech. Dig.

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