CMOS transistors with self-aligned planarization twin-well by us

Details CMOS transistors with self-aligned planarization twin-well by us CMOS transistors with self-aligned planarization twin-well by us

1998-03-31

1999-07-27

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257351, 257338, 438228, H01L 2976, H01L 2994

Patent

active

059294930

ABSTRACT:
The present invention discloses a structure for forming CMOS transistors with a self-aligned planarization twin-well by using fewer mask counts. An N-well is formed in the semiconductor substrate. Then, a P-well is formed against the N-well, and portion of the P-well is formed along the bottom of the N-well. An oxide region is formed on the surface of both the N- and P-wells, and covers portions of the N- and P-wells. A high energy and low dose boron blanket implantation is performed to increase the threshold voltage of the oxide region, which has been used for an ESD (Electro-Static Discharge) protection circuit. Punch-through stopping layers for the CMOS transistor are formed in the upper portion of the N-well. A BF.sub.2 ion implantation layer is formed at the top of both the N- and P-wells to increase the threshold voltages of the PMOSFET and NMOSFET transistors. A pad oxide layer is also formed to cover the top of the N- and P-wells, and portions of the pad oxide layer are then formed to be the gate oxide layer of the PMOSFET and NMOSFET transistors.

REFERENCES:
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patent: 5278441 (1994-01-01), Kang et al.
patent: 5329138 (1994-07-01), Mitani et al.
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5606191 (1997-02-01), Wang
Silicon Processing for the VLSI Era vol. 2--Process Integration, S. Wolf, pp. 389-397, 1990.

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