Self-aligned diffused source vertical transistors with stack cap

Details Self-aligned diffused source vertical transistors with stack cap Self-aligned diffused source vertical transistors with stack cap

1997-01-22

1999-07-27

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257302, 257303, 438248, 438386, 438396, H01L 29108, H01L 2976

Patent

active

059294779

ABSTRACT:
A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

REFERENCES:
patent: 4716548 (1987-12-01), Mochizuki
patent: 4774556 (1988-09-01), Fujii et al.
patent: 4796228 (1989-01-01), Baglee
patent: 4876580 (1989-10-01), Nishizawa
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4964080 (1990-10-01), Tzeng
patent: 4979004 (1990-12-01), Esquivel et al.
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5016067 (1991-05-01), Mori
patent: 5016068 (1991-05-01), Mori
patent: 5017977 (1991-05-01), Richardson
patent: 5071782 (1991-12-01), Mori
patent: 5078498 (1992-01-01), Kadakia et al.
patent: 5146426 (1992-09-01), Mukherjee et al.
patent: 5258634 (1993-11-01), Yang
patent: 5338953 (1994-08-01), Wake
patent: 5350937 (1994-09-01), Yamazaki et al.
patent: 5382540 (1995-01-01), Sharma et al.
patent: 5386132 (1995-01-01), Wong
patent: 5460994 (1995-10-01), Kim
patent: 5467305 (1995-11-01), Bertin et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5574299 (1996-11-01), Kim
Chang et al. (1980) "Vertical FET Random-Access Memories with Deep Trench Isolation" IBM Technical Disclosure Bulletin, 22 (8B): 3683-3687.
Frank et al. (1992) "Monte Carlo Simulation of a 30 nm Dual-Gate MOSFET: How Short Can Si Go?" IEEE: 21.1.1-21.1.4.
Hamamoto et al. (1995) "Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture for Ultra Low-Power Non-Destructive DRAMs" Symposium on VLSI Circuits Digest of Technical Papers: 79-80.
Hanafi et al. (1995) "A Scalable Low Power Verticle Memory" IEEE: 27.2.1-27.2.4.
Pein et al. (1993) "A 3-D Sidewall Flash EPROM Cell and Memory Array" IEEE Electron Device Letters 14(8): 415-417.
Pein et al. (1995) "Performance of the 3-D PENCIL Flash EPROM Cell and Memory Array" IEEE Transactions on Electron Devices, 42(11).
Tiwari et al. (1995) "Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage" IEEE: 20.4.1-20.4.4.

Affiliated with

Also associated with

Rating

Self-aligned diffused source vertical transistors with stack cap does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned diffused source vertical transistors with stack cap, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned diffused source vertical transistors with stack cap will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-881674