Memory circuit for reordering selected data in parallel with sel

Details Memory circuit for reordering selected data in parallel with sel Memory circuit for reordering selected data in parallel with sel

1997-05-09

1999-12-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711150, 711118, 711201, G06F 1200

Patent

active

060031190

ABSTRACT:
A cache memory comprising a plurality of memory locations and a multiplexer tree for accessing selected memory locations and reordering the data retrieved from the selected memory locations prior to outputting the data to the processor. The multiplexer tree is controlled by an adder/decoder circuit which generates an effective address from two address operands and causes the multiplexer tree to perform the steps of accessing the data and re-ordering the data at least partially in parallel, thereby reducing memory latency.

REFERENCES:
patent: 5353426 (1994-10-01), Patel et al.
patent: 5581719 (1996-12-01), Steely, Jr. et al.
patent: 5592634 (1997-01-01), Circello et al.
patent: 5608886 (1997-03-01), Blomgren et al.
patent: 5802602 (1998-09-01), Rahman et al.
patent: 5809272 (1998-09-01), Thusoo et al.

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