Static random access memory with reduced soft error rate

Details Static random access memory with reduced soft error rate Static random access memory with reduced soft error rate

1988-08-11

1989-11-07

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365203, 36518907, 371 211, G11C 1300

Patent

active

048796905

ABSTRACT:
A storage node in each of memory cells in a static RAM is connected to a bit line through an accessing MOSFET. The accessing MOSFET has its gate connected to a word line. A word line driver comprising a level shifting N channel MOSFET and a CMOS inverter is connected to the word line. At the time of selecting the word line, a potential which is lower, by a threshold voltage of the MOSFET, than a power-supply potential is applied to the word line. Thus, a sub-threshold current flowing in the MOSFET connected between the storage node for storing data at a high level and the bit line to which data of a high level is read out becomes substantially small, so that a potential of the storage node for storing data of a high level is not lowered.

REFERENCES:
patent: 4811294 (1989-03-01), Kobayashi et al.
Jap. J. Appl. Phys: "Soft Error Analysis of Fully Static MOS Ram", by Masahiko Yaoshimoto et al., vol. 22 (1983), Supplement 22-1, pp. 69-73.
IEEE J. of Sol. St. Circuits: "Influences on Sift Error Rates in Static Ram's", by Paul M. Carter et al., vol. SC-22, No. 3, Jun. 1987, pp. 430-436.

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