Process for fabrication of stacked, complementary MOS field effe

Details Process for fabrication of stacked, complementary MOS field effe Process for fabrication of stacked, complementary MOS field effe

1983-02-07

1984-08-28

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29576J, 29577C, 148187, 148188, H01L 21265, H01L 21225

Patent

active

044675186

ABSTRACT:
A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

REFERENCES:
patent: 4090915 (1978-05-01), Keller
patent: 4272880 (1981-06-01), Pashley
patent: 4305973 (1981-12-01), Yaron et al.
patent: 4335504 (1982-06-01), Lee
patent: 4351674 (1982-09-01), Yoshida et al.
Gibbons et al., IEEE Electron Device Letters, "One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon", vol. EDL-1, No. 6, Jun. 1980.

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