Received-data bit synchronization circuit

Details Received-data bit synchronization circuit Received-data bit synchronization circuit

1997-12-22

1999-12-14

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327107, 327144, H04L 700

Patent

active

060027312

ABSTRACT:
In a data synchronization circuit for obtaining a clock synchronized with bits of received data to submit the received data to retiming, it is achieved that a phase synchronization without use of a feedback loop configuration giving rise to oscillations is performed. The received data are devided according to the frequency in a frequency dividing circuit. This frequency divided output and the respective n-phase clocks are compared in phase to generate a specific signal to specify one of n-phase clocks having predetermined phase relations to the frequency divided output. While, on the other hand, the change points of the frequency divided output are synchronized with the extracted clock of a clock selector to average the specific signal with the timing of this change point synchronization signal. One of n-phase clocks is extracted in conformity with the state of this averaged output to make an extracted clock and to subject the received data to retiming in a flip-flop by using this clock.

REFERENCES:
patent: 4996444 (1991-02-01), Thomas et al.
patent: 5138633 (1992-08-01), Cortese
patent: 5341405 (1994-08-01), Mallard, Jr.
patent: 5608357 (1997-03-01), Ta et al.
patent: 5712580 (1998-01-01), Baumgartner et al.
patent: 5757857 (1998-05-01), Buchwald

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