Static random access memory device and manufacturing method ther

Details Static random access memory device and manufacturing method ther Static random access memory device and manufacturing method ther

1995-11-13

1999-01-05

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257904, 257644, H01L 2348

Patent

active

058567062

ABSTRACT:
A static random access memory device includes: a semiconductor substrate divided into a cell array portion and a periphery circuit portion; a first insulating layer for insulating devices formed on the substrate from a thin-film transistor; a conductive layer formed on the first insulating layer in the cell array portion, for supplying power; a buffer layer formed on the conductive layer in the cell array portion; a second insulating layer formed on the buffer layer in the cell array portion and on the first insulating layer of the periphery circuit portion; and a metal wiring pattern formed on the second insulating layer. A first portion of the metal wiring pattern connects to the conductive layer via a first contact hole which is formed passing through the second insulating layer and the buffer layer, thus exposing the conductive layer in the cell array portion. A second portion of the metal wiring pattern connects to the substrate via a second contact hole which is formed passing through the second insulating layer and the first insulating layer, thus exposing the semiconductor substrate in the periphery circuit portion or exposing a contact to a device in the semiconductor substrate in the cell array portion. The first and second portions of the metal wiring pattern may or may not connect to each other. The buffer layer prevents over-etching caused by the difference in the etched depth of the first and second contact holes which are concurrently formed, solving the problem of poor contact to the conductive layer from the metal wiring pattern formed on the second insulating layer.

REFERENCES:
patent: 5459354 (1995-10-01), Hara
patent: 5470793 (1995-11-01), Kalnitsky

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