Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1997-03-07
1998-10-06
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Data refresh
36523003, 36523006, 36523008, 365236, G11C 800
Patent
active
058187774
ABSTRACT:
A memory device includes address, data, and command busses, a bank of memory cells arranged in rows, an address decoder coupled to the address bus and memory bank, a read/write circuit coupled to the address decoder and memory bank, a data input/output circuit coupled to the data bus and read/write circuit, and a control circuit coupled to the command bus, address decoder, read/write circuit, and data input/output circuit. The control circuit implements a self refresh of the memory bank when it receives on the command bus a clock signal having clock edges, a refresh command at a first clock edge, and a column command at a second clock edge that occurs a predetermined number of clock edges after the first clock edge. The predetermined number is small enough so that previous versions of the memory device do not interpret the column command as a separate instruction.
REFERENCES:
patent: 5450364 (1995-09-01), Stephens, Jr. et al.
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5627791 (1997-05-01), Wright et al.
patent: 5636173 (1997-06-01), Schaefer
Micro)n Technology, Inc.
Nelms David C.
Phan Trong
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