Semiconductor storage device

Static information storage and retrieval – Read/write circuit – Noise suppression

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36523001, G11C 1300

Patent

active

058187731

ABSTRACT:
The invention provides a semiconductor storage device which reduces noise arising from a coupling capacitance between adjacent digit lines in a memory cell array region having multiple bit input and output terminals. A plurality of first and second digit line selection circuits connect first and second selection digit line pairs to first and second data buses, respectively, such that at least one of non-selected digit line pairs is interposed between a selected digit line pair selected by the first digit line selection circuits and another selected digit line pair selected by the second digit line selection circuits.

REFERENCES:
patent: 5010524 (1991-04-01), Fifiezo et al.
"A 5ns 32K.times.8/9 BiMOS TTL SRM with Alternated Bit Line Load Architecture", Technical Report of the Institute of Electronics, Information and Communication Engineers, Sep. 24, 1992.

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