Method of fabricating high speed CMOS devices

Details Method of fabricating high speed CMOS devices Method of fabricating high speed CMOS devices

1983-12-12

1985-05-28

Weisstuch, Aaron

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29590, 29591, 156653, 357 42, 357 67, H01L 21283

Patent

active

045191263

ABSTRACT:
In order to reduce the mechanical stress that occurs at the interface of a layer of a refractory metal silicide and a layer of silicon dioxide, it is proposed that a buffer layer of polycrystalline silicon be interposed between the two layers. To accomplish this and prior to forming contact openings, the buffer layer of polycrystalline silicon is deposited on the layer of silicon dioxide and the structure is then provided with an apertured mask to define the contact openings. The structure is then initially etched through both the buffer layer and the underlying layer of silicon dioxide in order to expose portions of the buried contact regions followed by a second etch of only the buffer layer to only expose portions of the layer of silicon dioxide in order to form a gate member and any required interconnects. The process further includes the formation of a layer of metal silicide on the interconnects, in the contact openings and on the gate member.

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"Beam-Lead Technology", M. P. Lepselter, The Bell System Tech. Journal, vol. XLV, No. 2, Feb. 1966, pp. 233-253.
"Reducing the Sheet Resistance . . . ", V. L. Rideout, IBM Technical Disclosure Bulletin, vol. 17, No. 6, Nov. 1974, pp. 1831-1833.
"SB-IGFET: An Insulated Gate . . . Source and Drain", M. P. Lepselter et al., Proc. IEEE-Letters , Aug. 1968, pp. 1400-1402.

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