Method of fabricating contact sites for microelectronic devices

Details Method of fabricating contact sites for microelectronic devices Method of fabricating contact sites for microelectronic devices

1997-10-30

1999-08-03

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438634, 438761, 438762, 438696, 438702, 438701, 438639, 438640, 438629, 438637, 438638, H01L 21265

Patent

active

059337559

ABSTRACT:
A contact site is formed for contacting a substrate adjacent an electrode formed on the substrate, the electrode and the substrate being separated by a first insulating layer formed on the substrate, the electrode having a top surface and a sidewall surface. A second insulating layer is formed which covers the top and sidewall surfaces of the electrode. A dielectric region is then formed on the second insulating layer, overlying the electrode and disposed adjacent an exposed portion of the second insulating layer which overlies a portion of the microelectronic layer laterally adjacent the electrode, the dielectric region having a sidewall surface adjacent the exposed portion of the second insulating layer. A third insulating layer is formed which covers the exposed portion of the second insulating layer and the sidewall surface of the dielectric region. Portions of the first, second and third insulating layers are then removed to expose a portion of the substrate adjacent the electrode while leaving the electrode covered. The dielectric region may be formed by forming an etching stop layer on the second insulating layer, forming a dielectric layer on the etching stop layer, and removing portions of the dielectric layer and the etching stop layer to expose a portion of the second insulating layer overlying a portion of the microelectronic layer laterally adjacent the electrode and to form a dielectric region and an etching stop region adjacent the exposed portion of the second insulating layer, the dielectric region and the etching stop regions having respective sidewall surfaces adjacent the exposed portion of the second insulating layer. The third insulating layer may be formed to cover the exposed portion of the second insulating layer and the sidewall surfaces of the dielectric and etching stop regions.

REFERENCES:
patent: 5084416 (1992-01-01), Ozaki et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5420077 (1995-05-01), Saito et al.
patent: 5484744 (1996-01-01), Hong
patent: 5565372 (1996-10-01), Kim

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