Deadlock avoidance in a split-bus computer system

Details Deadlock avoidance in a split-bus computer system Deadlock avoidance in a split-bus computer system

1997-07-30

1999-08-03

Sheikh, Ayaz R.

39518401, 39520054, G06F 1300

Patent

active

059336129

ABSTRACT:
A mechanism is provided for avoiding deadlock in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In accordance with another embodiment of the invention, the bus bridge detects when a state of the split-transaction bus would, if a protocol of said split-transaction bus were adhered to, result in deadlock. The bus bridge then drives one or more signals on the split-transaction bus in disregard of the protocol of the split-transaction bus, thereby avoiding deadlock. In accordance with still a further embodiment of the invention, transactions accepted within the bus bridge are monitored. When a combination of said transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. The predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock.

REFERENCES:
patent: 5442763 (1995-08-01), Bartfai et al.
patent: 5469435 (1995-11-01), Krein et al.
patent: 5473762 (1995-12-01), Kelly et al.
patent: 5542056 (1996-07-01), Jaffa et al.
patent: 5544332 (1996-08-01), Chen
patent: 5546546 (1996-08-01), Bell et al.
patent: 5592670 (1997-01-01), Pletcher
patent: 5680402 (1997-10-01), Olnowich et al.

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