Static information storage and retrieval – Read/write circuit – Testing
Patent
1993-05-05
1995-01-10
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
36523003, G11C 2900
Patent
active
053813723
ABSTRACT:
A semiconductor memory device has a plurality of memory cell arrays; input and output sections each provided so as to correspond to each of the memory cell arrays; and an allocating section provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.
REFERENCES:
patent: 4744061 (1988-05-01), Takomae
patent: 5202853 (1993-04-01), Choi
patent: 5243570 (1993-09-01), Saruwatari
Kozuka Eiji
Miyawaki Naokazu
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Zarabian A.
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-855860