Semiconductor memory device incorporating redundancy memory cell

Details Semiconductor memory device incorporating redundancy memory cell Semiconductor memory device incorporating redundancy memory cell

1993-09-07

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, G11C 2900

Patent

active

053813715

ABSTRACT:
In a semiconductor memory device including memory cells and redundancy memory cells, a redundancy decoder for accessing the redundancy memory cells and disabling a normal decoder for accessing the memory cells includes a test circuit for introducing a test signal into the redundancy decoder. When the test signal is active, the redundancy decoder is disabled in spite of receiving a redundancy address, and instead, the normal decoder is operated to thereby access the memory cells.

REFERENCES:
patent: 4714839 (1987-12-01), Chung
patent: 4860260 (1989-08-01), Saito et al.
patent: 5140554 (1992-08-01), Schreck et al.
patent: 5276360 (1994-01-01), Fujima

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